Titre: Post-modern C++ and C++17 abstractions for heterogeneous computing with Khronos OpenCL SYCL


Auteur : Ronan Keryell, Xilinx Research Labs
 
Abstract
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Computing architectures nowadays are huge multi-processor
system-on-chips with different kind of processors, GPU, configurable
specific accelerators (video CODEC...), reconfigurable programmable
logic (FPGA), various hierarchies of memory and memory interfaces,
configurable IO and network support, security support, power control,
etc. High-performance applications may use a hierarchy of such system
up to fill up a full-scale data-center.
 
So the programmer is facing now a fractal architecture, demanding also
more and more control for power efficiency. This tends to require a
dense fractal set of skills and tools.
 
OpenCL SYCL C++ is a new open standard from Khronos aiming at solving
some of the programming issues related to heterogeneous computing.
This pure C++17 domain-specific embedded language allows the
programmer to write single-source C++17 host code with accelerated
code expressed as functors. The data accesses are described with
accessor objects that implicitly define a task graph that can be
asynchronously scheduled on a distributed-memory system including
several CPU and accelerators.
 
Since this programming model is quite generic, we will end by
introducing some extensions we study at Xilinx to optimize FPGA usage
with the concept of pipes to define 1-to-1 connections between kernels
in the task graph without requiring expensive memory bandwidth.
 
As this talk is focused on C++, we will also introduce some
interesting features of C++17 and other C++ frameworks to address the
issue of heterogeneous computing.
 
 
Bio of the speaker:
-------------------
 
Ronan Keryell is principal software engineer at Xilinx Research Labs
in Dublin (Ireland), working on high-level programming models for FPGA
and is member of the Khronos OpenCL & SYCL C++ committee.
 
Ronan Keryell received his MSc in Electrical Engineering and PhD in
Computer Science from École Normale Supérieure of Paris & University
of Paris Sud (France), on the design of a massively parallel
RISC-based VLIW-SIMD graphics computer and its programming
environment. He was assistant professor in the Computer Science
department at MINES ParisTech and later at Télécom Bretagne (France),
working on automatic parallelization, compilation of PGAS languages
(High-Performance Fortran), high-level synthesis and co-design,
networking and secure computing. He was co-founder of 3 start-ups,
mainly in the area of High Performance Computing, and was the
technical lead of the Par4All automatic parallelizer at SILKAN,
targeting OpenMP, CUDA & OpenCL from sequential C & Fortran. Before
joining Xilinx, he worked at AMD on programming models for GPU.